1. Field of the Invention
The present invention relates to a peripheral circuit block of a semiconductor memory system having a high density memory matrix, and more particularly, to the layout of sense amplifiers connected to bit lines of the high density memory matrix.
2. Description of the Prior Art
Memory cell size can be reduced to about 1 .mu.m.times.1 .mu.m, considered to be the limit of current high density memory manufacturing accuracy, particularly in a dynamic RAM (Random Access Memory). But, a large scale integrated memory system with a bit line width of 1 .mu.m and inter-line interval of 1 .mu.m can also be produced. However, the peripheral circuit blocks, such as address decoders connected to the word lines or sense amplifiers connected to the bit lines cannot be accommodated within the minimum size of 1 .mu.m.times.1 .mu.m. This is because the peripheral circuit blocks comprise a large number of circuit elements. Currently, a sense amplifier is about 30 .mu.m wide and the bit line width is several microns. Therefore, when a memory matrix is integrated with particularly high density, it is geometrically impossible to arrange the peripheral circuit blocks in a line with the bit lines and word lines. But, when such an attempt is made, the results are that the routing of the bit lines extending from the memory matrix to the sense amplifier requires a large amount of chip area. This area, between the memory matrix and the row of sense amplifiers, is wasted area and used only for routing the bit lines. Moreover, the length of the extension of each bit line differs according to position within the memory matrix. This is particularly a problem in a dynamic RAM, where each memory cell comprises one transistor and one capacitor. Thus, the different capacity between bit lines is very undesirable.